Device for interpolating missing color-difference signal by averaging line-sequential color-difference signals

ABSTRACT

An apparatus interpolates color-difference line-sequential signals appearing alternately in a video signal together with a luminance signal. The video signal is received by an input circuit and then held temporarily and on a horizontal scanning line basis by a hold circuit. Each of the color-difference signals is interpolated by an interpolating circuit by producing an arithmetic mean of the color-difference data of the video signal being held by the hold circuit and color-difference data of the video signal being received by the input circuit, on the basis of the pixels corresponding to each other on horizontal scanning lines.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a video signal conversion apparatusand, more particularly, to an apparatus for interpolating acolor-difference line-sequential video signal.

2. Description of the Prior Art

A color-difference line-sequential color video signal system is usedwith an electronic still camera, a color-difference line-sequentialcolor television (TV) system, and others. As well known in the art, acolor-difference line-sequential color video signal system is such thattwo different kinds of color-difference signals appear alternately on ahorizontal scanning line basis. For example, in a certain system, one oftwo color-difference signals R-Y and B-Y appears on one scanning line,and the other on the next scanning line successively.

Some modern solid-state imaging devices are provided with a delaycircuit for delaying a color-difference signal by one horizontalscanning (1H) period before producing it, so that one missingcolor-difference signal is produced. Usually, such a delay circuit isconstructed to delay a color-difference signal by 1H period withoutapplying analog-to-digital conversion to the signal, the delayed signalthus composes the one missing color-difference signal. Hence, the sameline of the color-difference signal appears continuously over 2H period.

Generally a color-difference signal which is delayed by an analog delaycircuit as stated above is not of good quality since it containsabundance of noise. Insofar as an ordinary video monitor, usingtwo-field, one-frame interlace scanning system is used to reproduce avideo signal which contains such delayed signal components, the picturemay not appear so degraded. However, when it comes to a hard copy whichis produced by recording the picture, as represented by the videosignal, on a recording medium, the degradation in the quality of thepicture due to the deterioration of the signal is conspicuous. Such adegradation is more pronounced in still pictures than in moving picturesand in hard copies than in soft copies.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide anapparatus for interpolating a color-difference line-sequential videosignal which is capable of producing a video signal with a good picturequality.

In accordance with the present invention, there is provided an apparatusfor interpolating color-difference line-sequential signals which appearalternately in a video signal together with a luminance signal. Theapparatus comprisesinput means for receiving the video signal, holdingmeans for temporarily holding on a horizontal scanning line of the videosignal which is received by the input means; and interpolating means forproducing an arithmetic mean of color-difference data of the videosignal which is being held by the holding means and the color-differencedata of the video signal which is being received by the input means.Interpolation of each color-difference signal is based on the basis ofpixels which correspond to each other on horizontal scanning lines.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will become more apparent from the following detaileddescription taken in conjunction with the accompanying drawings inwhich:

FIG. 1 is a schematic block diagram showing a signal interpolatingapparatus in accordance with the present invention;

FIG. 2 is representative of the process of interpolation which isperformed by the apparatus of FIG. 1;

FIG. 3 is representative of the process of interpolation in accordancewith another embodiment of the present invention;

FIGS. 4A and 4B are views, similar to FIGS. 2A and 2B, showing anexample of color-difference signal interpolation which is implementedwith the principle of FIG. 3;

FIG. 5 is a schematic block diagram showing a specific arrangement forpracticing the process of FIG. 3;

FIGS. 6 and 7 show truth tables associated with an address controllerwhich is included in the arrangment of FIG. 5; and

FIG. 8 is a schematic block diagram showing an exemplary conditionwherein the arrangement of FIG. 5 is being supplied with a video signalon a scanning line #3 and delivering a video signal on a scanning line#2.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1 of the drawings, a signal interpolating apparatusembodying the present invention is shown. As shown, the apparatusincludes five delay circuits (1HDL) 10, 11, 12, 13 and 14. Inputterminals 16, 18 and 20 are interconnected, respectively, to three ofthe delay circuits, i.e. delay circuits 10, 11 and 13. The delay circuit10 comprises a digital delay circuit which receives luminance signalcomponents Y in a digital format from the input 16 and sequentiallytransfers them to an output 22 after delaying them by 1H period.

The delay circuit 11, like the delay circuit 10, comprises a digitaldelay circuit which receives color-difference signal components R-Y in adigital format and sequentially transfers them to an output 24 afterdelaying them by 1H period. The output 24 of the delay circuit 11 isinterconnected to the delay circuit 12 and one input terminal of aselector 26, which will be described later. Also comprising a digitaldelay circuit, the delay circuit 12 has an output 28 which isinterconnected to one input of an averaging circuit 30. The averagingcircuit 30 is in turn interconnected at the other input thereof to thecolor-difference signal input 18 and its output 32 is connected to theother input of the selector 26.

The averaging circuit 30 serves as an arithmetic mean circuit whichsums, on a pixel-by-pixel basis, video signals sequentially arriving atthe two inputs 28 and 18 which are offset by 2H period from each otherand produces at an input 32 a signal which is representative of theirmean value. The selector 26 is adapted to selectively transfer thesignals appearing at the two inputs 24 and 32 to an output 34 asinstructed by a select input (S).

As shown in FIG. 1, the other color-difference signal B-Y is applied viathe input 20 to a circuitry which is made up of the delay circuits 13and 14, an averaging circuit 40, a selector 44 and constructed andfunctioning in the same manner as the above-described circuitry assignedto the color-difference signal R-Y. The select input of each of theselectors 26 and 44 is interconnected to an output 50 of anotherselector 48. The selector 48 delivers to its output 50 either one of thesignals PAO and PAO which are applied to inputs 54 and 56, respectively,in response to a select input 52.

A video signal is applied to the input terminals 16, 18 and 20 insynchronism with a pixel clock. The video signal may comprise a signalwhich is read from solid-state imaging device or a signal which is readfrom a video floppy disk where pictures picked up by an electronic stillcamera are magnetically stored. In this particular embodiment, the videosignal is assumed to be in a frame video signal format which completesone frame of picture. For example, a video signal produced by theindividual photosensitive cells of an imaging device using acolor-difference line-sequential format is interpolated by a 1H analogdelay circuit in the apparatus to have the missing color-differencesignals inserted, then separated into a luminance signal Y andcolor-difference signals R-Y and B-Y; converted to digital signalsindividually; and fed to the input terminals 16, 18 and 20. It will beapparent to those skilled in the art that the illustrative embodiment isapplicable not only to a video signal which contains deterioratedcolor-difference components as described but also to a video signalwhich has color-difference components missing line-sequentially.

Applied to the inputs 54 and 56 of the selector 48, respectively, arecomplementary signals which are representative of the least significantbit PAO of a line address which in turn is representative of a verticalscanning position of one line, e.g. the least significant bit of aread/write address of a memory which stores one line of video signal. Itis to be noted that the least significant bit of a line address showswhether a horizontal scanning line is odd or even.

The selection of the input 54 or 56 is instructed by a signal R-Y/B-Ywhich is fed to the select input 52 of the selector 48. For example,when the color-difference signal R-Y is the original one contained inthe first horizontal scanning line of one frame of video signal enteringinto the apparatus, i.e, which had not passed through the analog delaycircuit of the imaging device, the selector 48 selects the input 54 inresponse to the signal R-Y/B-Y so that the selector 26 selects theoutput 24 of the delay circuit 11 and the selector 44, the output 42 ofthe averaging circuit 40. On the other hand, when the color-differencesignal B-Y is contained in the first horizontal scanning line as theoriginal color-difference signal, the selector 48 selects the otherinput 56 so that the selector 26 selects the output 32 of the averagingcircuit 30 and the selector 44, the output 36 of the delay circuit 13.The output 50 of the selector 48 may alternatively be of the kind whichswitches itself every 1H period so as to show which one of the signalsR-Y and B-Y currently appearing on the inputs 18 and 20 was notprocessed by the analog delay circuit.

The video signal appearing on the outputs 22, 34 and 46 may be stored ina frame memory, and afterwards, processed before being fed to anapparatus which uses the video signal. The apparatus to which the videosignal is applicable may advantageously comprise a device which isadapted to reproduce a picture represented by the video signal on acolor printing paper or like picture recording medium as a hard copy.Naturally, the apparatus may comprise a video monitor adapted for theproduction of a soft copy.

The operation of the apparatus arranged as shown in FIG. 1 will bedescribed with reference to FIG. 2 In FIG. 2, step (A) the numbersprovided at the top of the chart are representative of the numbers whichare assigned to the lines of a video signal, i.e., horizontal scanninglines, and therefore, they correspond to the transition of a videosignal with respect to time. For example, as shown in FIG. 2, step (A)assume that a luminance signal component or data, Y₀ on the first line,i.e., scanning line #0, is applied to the input 16, and an originalcolor-difference component or data, R-Y which has not passed through ananalog delay circuit of an imaging device and is represented by R₀ inFIG. 2, step (A), is applied to the input 18, each in synchronism with apixel clock. At this instance, the other color-difference component ordata, B-Y on the line #0, is fed to the input 20. This signal has beendelayed by the analog delay circuit and deteriorated by much noise. Suchdeteriorated color-difference data are represented by blanks in FIG. 2,step (A). It is also noted that the data corresponding to thedeteriorated color-difference data may even be missing. The luminancedata Y and the color-difference data R-Y and B-Y are fed, respectively,to the delay circuits 10, 11 and 13 to be held therein for 1H period.

In the next 1H period, luminance data Y₁ on the next line, i.e.,scanning line #1, is applied to the input 16, and the originalcolor-difference data B-Y, represented by B₁ in FIG. 2, step (A), isapplied to the input 20, each in synchronism with the pixel clock. Then,in this particular example, the selector 48 causes the selector 26 tochoose the input 24 of the delay circuit 11 and the selector 44 tochoose the input 42 of the averaging circuit 40.

Simultaneously, the luminance data Y₁ applied to the input 16 anddeteriorated color-difference data R₁, i.e., data produced by delayingthe color-difference data R₀ on the line #0 with the analog delaycircuit, are fed to the input 18. On the other hand, thecolor-difference data R₀ stored in the delay circit 11 is delivered tothe output 34 via the selector 26, and at the same time, the data istransferred to the delay circuit 12. As a result, during this 1H period,the luminance data Y₀ and the color-difference data R₀ on the line #0are produced, respectively, at the output 22 of the delay circuit 10 andat the output 34 of the selector 26, in synchronism with the pixelclock.

Further, during the subsequent 1H period, luminance data Y₂ on a thirdline, i.e., second scanning line #2, is applied to the input 16, andoriginal color-difference data R₂ associated therewith is applied to theinput 18, in synchronism with the pixel clock. At this time, theselector 48 causes the selector 26 to choose the output 32 of theaveraging circuit 30 and the selector 44 to choose the output 36 of thedelay circuit 13.

Upon the entry of the color-difference data R₂, the deterioratedcolor-difference data R₁ stored in the delay circuit 11 is shifted intothe delay circuit 12, while at the same time, the color-difference dataR₀ on the line #0 is produced at the output 28 of the delay circuit 12timed to the pixel clock. The averaging circuit 30, therefore, adds thecolor-difference data R₀ on the line #0, appearing on the input 28, andthe color-difference data R₂ on the line #2, appearing on the input 18in synchronism with the data R₀, to produce a color-difference data, R₀₂as shown in FIG. 2, step (B), at the output 32 which corresponds to amean value of the two data. The color-difference signal R₀₂ istransferred to the output 34 by way of the selector 26.

Timed to the procedure described above, deteriorated color-differencedata B₂ is fed to the input 20. At this instant, the data B₁ stored inthe delay circuit 13 is delivered to the output 46 via the selector 44,and, at the same time, it is shifted into the delay circuit 14. Hence,during this 1H, the luminance data Y₁ on the line #1 is produced at theoutput 22 of the delay circuit 10; the color-difference data R₀₂, thearithmetic means of the color-difference data R₀ and R₂ on the lines #0and #2, is produced at the output 34 of the selector 26; and thecolor-difference data B₁ on the line #1 is produced at the output 46 ofthe selector 44, each in synchronism with the pixel clock.

Thereafter, the delivery of color-difference data, delayed by 1H period,and the color-difference data which are representative of an arithmeticmean are repeated alternately for each of the two different kinds ofcolor-difference signals R-Y and B-Y. Eventually, the color-differencedata as shown in FIG. 2, step (B), appear at the output 34 and 46 of theselectors 26 and 44. The luminance data Y, at the other hand, appear onthe output 22 after being delayed sequentially by 1H.

Considering the luminance and color-difference data on a line #n, forgeneralization, the procedure as described above may be expressed asfollows:

    Y.sub.n =Y.sub.n-1

    R.sub.n =R.sub.n-1 or (R.sub.n- 2+R.sub.n)/2

    B.sub.n (B.sub.n-2 +B.sub.n)/2 or B.sub.n-1

As stated above, in accordance with this particular embodiment, inferiorchrominance data, inserted by an analog delay circuit of an imagingdevice, are not used, and instead, the color-difference data, delayed bydigital processing, are used to produce their arithmetic means. Thissuccessively forms color-difference signals of superior quality. When ahard copy of a picture is produced by using a video signal whosecolor-difference signals have been interpolated as stated above, apicture which is pleasant to the eye is achieveable.

The interpolation of the color-difference signals, based on thearithmetic mean scheme as described above, may alternatively bepracticed by assigning two memory units to each of the twocolor-difference signals, each memory unit being capable of storing 2Hof color-difference data; one of the paired memory units is in a writemode while the other is in a read mode. Another embodiment of thepresent invention with such an alternative implementation will bedescribed with reference to FIG. 3 and FIGS. 4A and 4B.

In this alternative embodiment, memory units 100 and 101 are adapted tostore the color-difference signal R-Y, and memory units 102 and 103 areadapted to store the color-difference signal B-Y. The memory unit 100has a large enough capacity to store, for example, up to 2H of data,each being produced by coding color-difference data R-Y in each pixelinto a stream of eight bits, and it is made up of two discrete areas100a and 100b. The other memory units 101 to 103 are identical incapacity and construction as the memory unit 100.

In operation, during the first 1H period of one frame of the videosignal, the color-difference data R₀ on the line # is written into thearea 100a of the memory unit 100, while at the same time, the othercolor-difference data, B₀ on the same line is written into an area 102aof the memory unit 102, as shown in FIG. 2, step (A). It is assumed thatthe color-difference data R₀ is the original one, and thecolor-difference data B₀ is the deteriorated one which is the 1H delayedversion of color-difference data on the immediately preceding line asproduced by an analog delay circuit. In FIG. 3, steps (A) to (E), suchdeteriorated color-difference data are parenthesized such as (B₀) fordistinction purpose.

As shown in FIG. 3, step (B), during the next 1H period, the memory unit100 is switched to a read (R) mode and the memory uni 101 to a write (W)mode. The memory units 102 and 103, on the other hand, are held in theirexisting read/write modes. Deteriorated color-difference data (R₁) onthe line #1 arriving during this 1H period, is written into an areas101b of the memory unit 101, while at the same time, color-differencedata B₁ on that line is written into an area 102b of the memory unit102. Associated with these signals is the luminance data Y₁ on the line#1. In the meantime, the content of the area 100a of the memory unit100, i.e., color-difference data R₀ on the line #0, is read out.Associated with this data R₀ is the luminance data Y₀ on the line #0.

During the third 1H period, as shown in FIG. 3, step (C), the memoryunit 102 is switched to the read mode and the memory unit 103 to thewrite mode. The other memory units 100 and 101 are maintained in theirexisting read/write modes. The original color-difference data R₂,arriving during this period, is written into the area 101a of the memoryunit 101, and the deteriorated color-difference data (B₂) on that lineis written into an area 103a of the memory unit 103. It is the luminancedata Y₂ on the line #2 that is associated with the data R₂ and (B₂). Thecontent of the area 100a of the memory unit 100, i.e., color-differencedata R₀ on the line #, is read out again. Then, an arithmetic means ofthe two color-difference data R₂ and R₀ is produced to provide data R₀.Further, the content of the area 102b of the memory unit 102, i.e.,color-difference data B₁ on the line #1, is read out during this period.Color-difference data Y₂ on the line #2 is associated with thosesignals.

Thereafter, the read-out of 1H delayed color-difference data and thearithmetic operation for producing a means of color-difference dataappearing 2H before and current color-difference data are repeatedalternately for each of the two different kinds of color-differencesignals R-Y and B-Y. By using such a procedure, color-difference signalsinterpolated, as shown in FIG. 4B, are achieved. As a result theluminance signal Y data which appeared 1H before is produced.

Referring to FIG. 5, a specific circuit arrangement for implementing thefunction as described above with reference to FIG. 3 and FIGS. 4A and 4Bis shown. In FIG. 5, the same or similar structural elements as thoseshown in FIG. 1 are designated by like reference numerals. As shown, theinput terminal 18 is interconnected to the inputs of two 2H memory units100 and 101 as well as to one input terminal of the averaging circuit30. The outputs 105 of the memory units 100 and 101 are interconnectedto the other input of the averaging circuit 30 and the input of theselector 26. Likewise, the input terminal 20 is interconnected to theinputs of two 2H memory units 102 and 103 and one input of the averagingcircuit 40. Further, the outputs 107 of the memory units 102 and 103 areinterconnected to the other input of the averaging circuit 40 and theinput of the selector 44. The memory units 100 to 103 are implementedwith standard SRAMs.

The write addresses (WA) and the read addresses (RA) of the memory units100 to 103 are controlled by an address controlled 109. Specifically,the address controller 109 functions to generate addresses WA and RA aswell as select signals RSEL and BSEL in response to input signals RYSand PAO. While the input signal RYS shows the kind of the originalcolor-difference signal, B-Y or R-Y, which is contained in the linebeing received, the input PAO is representative of the least significantbit of a line address.

As shown in the truth table of FIG. 6, the write address WA of each ofthe memory units 100 to 103 assumes the most significant bit whichcorresponds to the least significant bit PAO of a line address.Regarding the most significant bit of a read address RA of each of thememory units 100 to 103 although it also assumes a value whichcorresponds to the least significant bit of a line address, thecolor-difference signal R-Y and B-Y are opposite to each other withrespect to their values, as shown in a truth table of FIG. 7. The mostsignificant bit of the write address WA or the read address RAdesignates, for example, the areas 100a to 103a of the memory units 100to 103 when it is ZERO and the areas 100b to 103b when it is ONE. Withthis construction, the embodiment of FIG. 5 accomplishes the switchingof the memory units as described with reference to FIG. 3, steps (A) to(E).

In the embodiment of FIG. 5, the selector 26 is adapted to select eitherthe outputs of the memory units 100 and 101 or the output of theaveraging circuit 30. Likewise, the selector 26 serves to select eitherthe outputs of the memory units 102 and 103 or the output of theaveraging circuit 40. Such selection is instructed by the outputs RSELand BSEL of the address controller 109.

The luminance signal input terminal 16 is interconnected to two memoryunits 111 and 112 and the outputs of which are interconnected to theluminance signal output terminal 22. Basically, each of the memory units111 and 112 may be implemented with a digital memory having a capacitywhich is large enough to accommodate 1H of luminance data. In thisparticular embodiment, however, the memory units 111 and 112 areimplemented with SRAMs similar to ones used in the other memory units100 to 103.

The address controller 109 generates the write and read addresses WA andRA as well as the select signals RSEL and BSEL based on the logic asshown in FIGS. 6 and 7, such that when the memory units 100 to 103 and111 and 112 are in an input condition as shown in FIG. 3, step (A), anoutput condition as shown in FIG. 3, step (B), is set up.

FIG. 8 shows, by way of example, a condition wherein a video signal onthe line #3 is received by the apparatus and a video signal on the line#2 is produced from the same, i.e., a condition which corresponds toFIG. 3, step (D). As shown, the color-difference signal R-Y, data R₂, isselected by the data selector 26 while with respect to thecolor-difference signal B-Y, an output of the averaging circuit 40 isselected by the data selector 44. In this example, the output of theaveraging circuit 40 comprises an arithmetic mean B₁₃ ofcolor-difference data B₁ stored in the area 103b and color-differencedata B₃ appearing at the input 20. The luminance signal Y, on the otherhand, is read out of the memory units 111 and 112 alternately so as tobe matched in phase to the color-difference signals.

This particular embodiment advantageously features hardware on a smallerscale, compared to the embodiment of FIG. 1. Specifically, while theembodiment of FIG. 1 needs five delay circuits, FIG. 5 needs only threepairs of memory units. In addition, because the embodiment of FIG. 5 isconstructed to synchronize the timing of the output video signal bycontrolling the most significant bits of the addresses of the memoryunits, interpolation can be accomplished by repeating such a controloperation, and therefore, the construction of the memory control circuitis remarkably simple.

In summary, it has been seen that the present invention is capable ofproducing a video signal of good quality on an arithmetic mean basis byuse of digitally delayed color-difference signals instead ofcolor-difference signals of poor quality which are subjected to analogdelay. A hard copy of a picture which is represented by such a videosignal is pleasant to the eye.

What is claimed is:
 1. An apparatus for receiving consecutive videosignals, each video signal representing data for a plurality of pixelson a horizontal scanning line and including a luminance signal and oneof two possible color-difference signals, the two possiblecolor-difference signals appearing alternately within the consecutivevideo signals, and for interpolating the other of the two possiblecolor-difference signals in the video signal, comprising:input means forreceiving the consecutive video signals; holding means, operativelyconnected to said input means, for temporarily holding the horizontalscanning line of each said video signal being received by said inputmeans; and interpolating means, operatively connected to said holdingmeans and said input means, for producing an arithmetic mean of thecolor-difference signal of the video signal being held by said holdingmeans and the color-difference signal of a next video signalsimultaneously being received by said input means on a pixel to pixelbasis, said pixels of one horizontal scanning line corresponding to thepixels of the next horizontal scanning line, thereby interpolating themissing color-difference signal; said holding means including,firstdelay means, operatively connected to said input means, for delaying byone horizontal scanning period the color-difference signal of the videosignal being received by said input means, and second delay means,operatively connected to said first delay means, for further delaying byone horizontal scanning period the color-difference signal having beendelayed by said first delay means; said interpolating means including,arithmetic mean means, operatively connected to said input means andsaid second delay means, for producing an arithmetic mean of an outputof said second delay means and an output of said input means, andselecting means, operatively connected to said arithmetic mean means andsaid first delay means, for selecting alternately either an output ofsaid first delay means or an output of said arithmetic means.
 2. Theapparatus as claimed in claim 1, further comprising luminance delaymeans for delaying by one horizontal scanning period the luminancesignal of the video signal being received by said input means.
 3. Theapparatus as claimed in claim 1, wherein the color-difference signalbeing received by said input means includes either an R-Y or a B-Ycolor-difference signal;said first and second delay means and saidarithmetic mean means operate upon the R-Y color-difference signal; saidholding means further including,third delay means, operatively connectedto said input means, for delaying by one horizontal scanning period theB-Y color-difference signal being received by said input means, andfourth delay means, operatively connected to said third delay means, forfurther delaying by one horizontal scanning period the B-Ycolor-difference signal having been delayed by said third delay means;said interpolating means further including,additional arithmetic meanmeans, operatively connected to said input means and said fourth delaymeans, for producing an arithmetic mean of an output of said fourthdelay means and an output of said input means, and additional selectingmeans, operatively connected to said third delay means and saidadditional arithmetic mean means, for selecting alternately either anoutput of said additional arithmetic mean means or an output of saidthird delay means; said selecting means reversing the alternateselection of the outputs of said first delay means and said arithmeticmean means upon terminating of the horizontal scanning lines; and saidadditional selecting means reversing the alternate selection of theoutputs of said additional arithmetic mean means and said third delaymeans upon terminating of the horizontal scanning line.
 4. An apparatusfor receiving consecutive video signals, each video signal representingdata for a plurality of pixels on a horizontal scanning line andincluding a luminance signal and one of two possible color-differencesignals, the two possible color-difference signals appearing alternatelyin the consecutive video signals, and for interpolating thecolor-difference signal which is missing from the video signal,comprising:input means for consecutively receiving the video signal;holding means operatively connected to said input means, for holdingtemporarily the video signal being received by said input means; andinterpolating means, operatively connected to said input means and saidholding means, for producing an arithmetic mean of the color-differencesignal of the video signal being held by said holding means and thecolor-difference signal of another video signal being simultaneouslyreceived by said input means on a pixel to pixel basis, the pixels ofone horizontal scanning line corresponding to the pixels of the otherhorizontal scanning line, thereby interpolating the missingcolor-difference signal; said holding means including,first and secondmemory circuits, said first and second memory circuits each having astorage capacity large enough for storing two horizontal scanning linesof color difference data of the video signals being received by saidinput means; said interpolating means including, arithmetic mean means,operatively connected to said first and second memory circuits and saidinput means, for producing an arithmetic mean of either an output ofsaid first memory circuit or an output of said second memory circuit andan output of said input means, and control means, operatively connectedto said first and second memory circuits, for controlling said first andsecond memory circuits and for selecting either the output of said firstmemory circuit or the output of said second memory circuit or the outputof said arithmetic means; said control means alternately writing thecolor-difference data of the video signal received by said input meansin said first and second memory circuits during each horizontalscanning, while maintaining the color-difference data of the priorhorizontal scanning period in the memory circuit which thecolor-difference data is not being written into; said control meansloading said arithmetic mean means with the color-difference dataappearing two horizontal scanning periods before from either said firstor second memory circuits; said control means selecting during onehorizontal scanning period the output of said arithmetic mean means, andduring the next one horizontal scanning period selecting thecolor-difference data appearing one horizontal scanning period beforefrom either said first or second memory circuits; and said control meansrepeating the alternate selection of the output of said arithmetic meanmeans and the selection of the color-difference data during eachhorizontal scanning period.
 5. The apparatus as claimed in claim 4,further comprising luminance delay means for delaying by one horizontalscanning period the luminance signal of the video signal which isreceived by said input means.
 6. The apparatus as claimed in claim 4,wherein the color difference signal is either a R-Y or a B-Ycolor-difference signal;said first and second memory circuits and saidarithmetic mean means operate upon the R-Y color-difference signals;said holding means further includingthird and fourth memory circuits,said third and said fourth memory circuits each having a storagecapacity large enough to store two horizontal scanning lines of the B-Ycolor-difference signal being received by said input means; saidinterpolating means further including, additional arithmetic mean means,operatively connected to said third and fourth memory circuits and saidinput means, for producing an arithmetic mean of an output of eithersaid third or fourth memory circuits and the output of said input means,and control means, for controlling said third and fourth memory circuitsand for selecting either the output of said additional arithmetic meanmeans or the outputs of said third and fourth memory circuits; saidcontrol means writing the B-Y color-difference signal received by saidinput means into either said third or fourth memory circuits during eachhorizontal scanning period while maintaining the B-Y color-differencesignal of the prior horizontal scanning period in the memory circuit inwhich the B-Y color different signal is not being written into; saidcontrol means loading said additional arithmetic mean means with the B-Ycolor-difference signal appearing two horizontal scanning periods beforefrom either said third or fourth memory circuit; said control meansselecting during one horizontal scanning period the output of saidadditional arithmetic mean means and during the next one horizontalscanning period selecting the B-Y color-difference signal appearing onehorizontal scanning period before from either said third or fourthmemory circuits; said control means repeating the alternate selection ofthe output of said additional arithmetic mean means and the selection ofB-Y color-difference signal during each horizontal scanning period; saidcontrol means reversing the alternate selection of the outputs of eithersaid first or second memory circuits or said arithmetic mean means uponterminating of the horizontal scanning line; and said control meansreversing the alternate selection of the outputs of either saidadditional arithmetic mean means or said third or fourth memory circuitsupon terminating of the horizontal scanning line.